Technical Reference Manual 002-29852 Rev. *B
2.3.9.6.37 CANFD_CH_TXBRP
Description:
Tx Buffer Request Pending
Address:
0x405200CC
Offset:
0xCC
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name TRP [7:0]
Bits 15 14 13 12 11 10 9 8
Name TRP [15:8]
Bits 23 22 21 20 19 18 17 16
Name TRP [23:16]
Bits 31 30 29 28 27 26 25 24
Name TRP [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:31 TRP R RW 0 Transmission Request Pending
Each Tx Buffer has its own Transmission Request
Pending bit. The bits are set via register TXBAR.
The bits are reset after a requested transmission has
completed or has been cancelled via register
TXBCR.
TXBRP bits are set only for those Tx Buffers
configured via TXBC. After a TXBRP bit has been set,
a Tx scan (see Section 3.5, Tx Handling) is started to
check for the pending Tx request with the
highest priority (Tx Buffer with lowest Message ID).
A cancellation request resets the corresponding
transmission request pending bit of register
TXBRP. In case a transmission has already been
started when a cancellation is requested, this is
done at the end of the transmission, regardless
whether the transmission was successful or not. The
cancellation request bits are reset directly after the
corresponding TXBRP bit has been reset.
After a cancellation has been requested, a finished
cancellation is signaled via TXBCF
after successful transmission together with the
corresponding TXBTO bit
when the transmission has not yet been started at the
point of cancellation
when the transmission has been aborted due to lost
arbitration
when an error occurred during frame transmission
In DAR mode all transmissions are automatically
cancelled if they are not successful. The
corresponding TXBCF bit is set for all unsuccessful
transmissions.
0= No transmission request pending
1= Transmission request pending
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers
To Next Page
Loading...
