Infineon TRAVEO T2G - 2.3.9.6.49 CANFD_CH_TTOCF

Technical Reference Manual 002-29852 Rev. *B
2.3.9.6.49 CANFD_CH_TTOCF
Description:
TT Operation Configuration
Address:
0x40520108
Offset:
0x108
Retention:
Retained
IsDeepSleep:
No
Comment:
Protected Write.
Default:
0x10000
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name LDSDL [7:5] TM [4:4] GEN [3:3] None [2:2] OM [1:0]
Bits 15 14 13 12 11 10 9 8
Name EECS
[15:15]
IRTO [14:8]
Bits 23 22 21 20 19 18 17 16
Name AWL [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:27] EVTP
[26:26]
ECC [25:25] EGTF
[24:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:1 OM RW R 0 Operation Mode
00= Event-driven CAN communication, default
01= TTCAN level 1
10= TTCAN level 2
11= TTCAN level 0
3 GEN RW R 0 Gap Enable
0= Strictly time-triggered operation
1= External event-synchronized time-triggered
operation
4 TM RW R 0 Time Master
0= Time Master function disabled
1= Potential Time Master
5:7 LDSDL RW R 0 LD of Synchronization Deviation Limit
The Synchronization Deviation Limit SDL is configured
by its dual logarithm LDSDL with SDL =
2(LDSDL + 5). It should not exceed the clock tolerance
given by the CAN bit timing configuration.
0x0-7 LD of Synchronization Deviation Limit (SDL <=
32...4096)
8:14 IRTO RW R 0 Initial Reference Trigger Offset
0x00-7F Positive offset, range from 0 to 127
15 EECS RW R 0 Enable External Clock Synchronization
If enabled, TUR configuration (TURCF.NCL only) may
be updated during TTCAN operation.
0= External clock synchronization in TTCAN Level 0,2
disabled
1= External clock synchronization in TTCAN Level 0,2
enabled
106
2022-04-18
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