Infineon TRAVEO T2G - 22.5.1.8.4 PROT_SMPU_SMPU_STRUCT_ATT1

Technical Reference Manual 002-29852 Rev. *B
22.5.1.8.4 PROT_SMPU_SMPU_STRUCT_ATT1
Description:
SMPU region attributes 1 (master structure)
Address:
0x40232024
Offset:
0x24
Retention:
Retained
IsDeepSleep:
No
Comment:
This register defines SMPU access control.
Default:
0x7000109
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:7] NS [6:6] PX [5:5] PW [4:4] PR [3:3] UX [2:2] UW [1:1] UR [0:0]
Bits 15 14 13 12 11 10 9 8
Name PC_MASK
_0 [8:8]
Bits 23 22 21 20 19 18 17 16
Name PC_MASK_15_TO_1 [23:16]
Bits 31 30 29 28 27 26 25 24
Name ENABLED
[31:31]
PC
_MATCH
[30:30]
None
[29:29]
REGION_SIZE [28:24]
Bit-fields
Bits
Name SW HW Default or
Enum
Description
0 UR R R 1 User read enable:
'0': Disabled (user, read accesses are NOT allowed).
'1': Enabled (user, read accesses are allowed).
Note that this register is constant '1'; i.e. user read
accesses are ALWAYS allowed.
1 UW RW R Undefined User write enable:
'0': Disabled (user, write accesses are NOT allowed).
'1': Enabled (user, write accesses are allowed).
2 UX R R 0 User execute enable:
'0': Disabled (user, execute accesses are NOT
allowed).
'1': Enabled (user, execute accesses are allowed).
Note that this register is constant '0'; i.e. user execute
accesses are NEVER allowed.
3 PR R R 1 Privileged read enable:
'0': Disabled (privileged, read accesses are NOT
allowed).
'1': Enabled (privileged, read accesses are allowed).
Note that this register is constant '1'; i.e. privileged
read accesses are ALWAYS allowed.
4 PW RW R Undefined Privileged write enable:
'0': Disabled (privileged, write accesses are NOT
allowed).
'1': Enabled (privileged, write accesses are allowed).
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2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers