Infineon TRAVEO T2G - 23.9.3 SCB_CMD_RESP_CTRL

Technical Reference Manual 002-29852 Rev. *B
23.9.3 SCB_CMD_RESP_CTRL
Description:
Command/response control
Address:
0x40600008
Offset:
0x8
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name BASE_RD_ADDR [7:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:9] BASE_RD
_ADDR
[8:8]
Bits 23 22 21 20 19 18 17 16
Name BASE_WR_ADDR [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:25] BASE_WR
_ADDR
[24:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:8 BASE_RD_ADDR RW R 0 I2C/SPI read base address for CMD_RESP mode. At
the start of a read transfer this BASE_RD_ADDR is
copied to CMD_RESP_STATUS.CURR_RD_ADDR.
This field should not be modified during ongoing bus
transfers.
16:24 BASE_WR_ADDR RW R 0 I2C/SPI write base address for CMD_RESP mode. At
the start of a write transfer this BASE_WR_ADDR is
copied to CMD_RESP_STATUS.CURR_WR_ADDR.
This field should not be modified during ongoing bus
transfers.
1388
2022-04-18
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