Infineon TRAVEO T2G - 23.9.33 SCB_INTR_I2 C_EC_MASKED

Technical Reference Manual 002-29852 Rev. *B
23.9.33 SCB_INTR_I2C_EC_MASKED
Description:
Externally clocked I2C interrupt masked
Address:
0x40600E8C
Offset:
0xE8C
Retention:
Retained
IsDeepSleep:
No
Comment:
When read, this register reflects a bitwise and between the interrupt request and mask
registers. This register allows SW to read the status of all mask enabled interrupt causes with
a single load operation, rather than two load operations: one for the interrupt causes and one
for the masks. This simplifies Firmware development. The associated interrupt is active ('1'),
when INTR_I2C_EC_MASKED != 0.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:4] EZ_READ
_STOP
[3:3]
EZ_WRITE
_STOP
[2:2]
EZ_STOP
[1:1]
WAKE_UP
[0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 WAKE_UP R W 0 Logical and of corresponding request and mask bits.
1 EZ_STOP R W 0 Logical and of corresponding request and mask bits.
2 EZ_WRITE_STOP R W 0 Logical and of corresponding request and mask bits.
3 EZ_READ_STOP R W 0 Logical and of corresponding request and mask bits.
1431
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers