Infineon TRAVEO T2G - 11.1 Register Details; 11.1.1 EFUSE_DATA_CUSTOMER_DATA

Technical Reference Manual 002-29852 Rev. *B
11.1 Register Details
11.1.1 EFUSE_DATA_CUSTOMER_DATA
Description:
Available EFUSE bits for customer usage.They can be programmed in NORMAL protection
state via CMx/DAP and in SECURE protection state via CMx.
Address:
0x402C0868
Offset:
0x68
Retention:
Retained
IsDeepSleep:
No
Comment:
The eFUSE memory consists of an array of eFUSE macros. The memory can only be read
with AHB-Lite Byte read transfers. A non-Byte AHB-Lite read transfer results in an AHB-Lite
bus error. An AHB-Lite write transfer results in an AHB-Lite bus error. Furthermore, an AHB-
Lite read transfer while a program operation is in progress (CMD.START is '1') results in an
AHB-Lite bus error.
The number of eFUSE memory Bytes is determined by the EFUSE_NR configuration
parameter. This parameter specifies the number of instantiated eFUSE macros. Each macro
has 16 Bytes. E.g., if EFUSE_NR is 8, the eFUSE memory has 8*16 Bytes = 128 Bytes.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name DATA_BYTE [7:0]
Bits 15 14 13 12 11 10 9 8
Name DATA_BYTE [15:8]
Bits 23 22 21 20 19 18 17 16
Name DATA_BYTE [23:16]
Bits 31 30 29 28 27 26 25 24
Name DATA_BYTE [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:31 DATA_BYTE RW R 0 Available EFUSE bits for customer usage.They can be
programmed in NORMAL protection state via
CMx/DAP and in SECURE protection state via CMx.
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2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers