Infineon TRAVEO T2G - 3.8.2 BP; 3.8.2.1 CM0 P_BP_BP_CTRL

Technical Reference Manual 002-29852 Rev. *B
3.8.2 BP
3.8.2.1 CM0P_BP_BP_CTRL
Description:
Breakpoint Unit Control
Address:
0xE0002000
Offset:
0x0
Retention:
Retained
IsDeepSleep:
No
Comment:
Provides BPU implementation information, and the global enable for the BPU.
Default:
0x40
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name NUM_CODE [7:4] None [3:2] KEY [1:1] ENABLE
[0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 ENABLE RW R 0 Enables the BPU:
0 BPU is disabled.
1 BPU is enabled.
1 KEY RW R 0 RAZ on reads, SBO for writes. If written as zero, the
write to the register is ignored.
4:7 NUM_CODE R 4 The number of breakpoint comparators. If
NUM_CODE is zero, the implementation does not
support any comparators.
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2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers