Infineon TRAVEO T2G - 3.8.7.8 CM0 P_MTB_DARCH

Technical Reference Manual 002-29852 Rev. *B
3.8.7.8 CM0P_MTB_DARCH
Description:
Device Architecture register
Address:
0xF0003FBC
Offset:
0xFBC
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x47700A31
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name ARCH_ID [7:0]
Bits 15 14 13 12 11 10 9 8
Name ARCH_ID [15:8]
Bits 23 22 21 20 19 18 17 16
Name RES_20
[20:20]
REVISION [19:16]
Bits 31 30 29 28 27 26 25 24
Name ARCHITECT [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:15 ARCH_ID R R 2609 Basic Trace Router Architecture
Major Architecture Revision 0
16:19 REVISION R R 0 Minor Architecture Revision
20 RES_20 R R 1 Reserved
21:31 ARCHITECT R R 571 Architect ARM
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2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers