Infineon TRAVEO T2G - 4.13.4 SCS; 4.13.4.1 CM4_SCS_ACTLR

Technical Reference Manual 002-29852 Rev. *B
4.13.4 SCS
4.13.4.1 CM4_SCS_ACTLR
Description:
Auxiliary Control Register
Address:
0xE000E008
Offset:
0x8
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name VALUE [7:0]
Bits 15 14 13 12 11 10 9 8
Name VALUE [15:8]
Bits 23 22 21 20 19 18 17 16
Name VALUE [23:16]
Bits 31 30 29 28 27 26 25 24
Name VALUE [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:31 VALUE RW R 0 Refer the following ARM documents for details about
CPU register descriptions:
ARMV7M :
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0403e.d/index.html
CM4 TRM :
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.100166_0001_00_en/index.html
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2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers