Technical Reference Manual 002-29852 Rev. *B
18.13.2 LIN_TEST_CTL
Description:
Test control
Address:
0x40500004
Offset:
0x4
Retention:
Retained
IsDeepSleep:
No
Comment:
This register support test functionality.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:5] CH_IDX [4:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:17] MODE
[16:16]
Bits 31 30 29 28 27 26 25 24
Name ENABLED
[31:31]
None [30:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:4 CH_IDX RW R 0 Specifies the channel index of the channel to which
test applies. The channel IO signals of channel indices
CH_IDX and CH_NR-1 are connected as specified by
MODE. CH_IDX should be in the range [0, CH_NR-2],
as channel index CH_NR-1 is always involved in test
and cannot be connected to itself. The test mode
allows BOTH of the two connected channels to be
tested.
Note: this testing functionality simplifies SW
development, but may also be used in the field to
verify correct channel functionality.
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers
To Next Page
Loading...
