Technical Reference Manual 002-29852 Rev. *B
26.8.7 CLK_CAL_CNT2
Description:
Clock Calibration Counter 2
Address:
0x4026014C
Offset:
0x14C
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name CAL_COUNTER2 [7:0]
Bits 15 14 13 12 11 10 9 8
Name CAL_COUNTER2 [15:8]
Bits 23 22 21 20 19 18 17 16
Name CAL_COUNTER2 [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:23 CAL_COUNTER2 R RW 0 Up-counter clocked on fast clock output #1 (see
CLK_OUTPUT_FAST). When
CLK_CAL_CNT1.CAL_COUNTER_DONE==1, the
counter is stopped and can be read by SW. Do not
read this value unless CAL_COUNTER_DONE==1.
The expected final value is related to the ratio of clock
frequencies used for the two counters and the value
loaded into counter 1:
CLK_CAL_CNT2.COUNTER=(F_cnt2/F_cnt1)*(CLK_CAL_CNT1.COUNTER)
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers