Infineon TRAVEO T2G - 17.17.2.4 IPC_INTR_STRUCT_INTR_MASKED

Technical Reference Manual 002-29852 Rev. *B
17.17.2.4 IPC_INTR_STRUCT_INTR_MASKED
Description:
Interrupt masked
Address:
0x4022100C
Offset:
0xC
Retention:
Not Retained
IsDeepSleep:
No
Comment:
When read, this register reflects 'a bitwise AND' between the INTR and INTR_MASK registers.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name RELEASE [7:0]
Bits 15 14 13 12 11 10 9 8
Name RELEASE [15:8]
Bits 23 22 21 20 19 18 17 16
Name NOTIFY [23:16]
Bits 31 30 29 28 27 26 25 24
Name NOTIFY [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:15 RELEASE R W 0 Logical and of corresponding request and mask bits.
16:31 NOTIFY R W 0 Logical and of corresponding INTR and INTR_MASK
fields.
1036
2022-04-18
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