Infineon TRAVEO T2G - 5.1.2 CPUSS_CM4_STATUS

Technical Reference Manual 002-29852 Rev. *B
5.1.2 CPUSS_CM4_STATUS
Description:
CM4 status
Address:
0x40200004
Offset:
0x4
Retention:
Not Retained
IsDeepSleep:
No
Comment:
Default:
0x13
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:5] PWR
_DONE
[4:4]
None [3:2] SLEEPDEEP
[1:1]
SLEEPING
[0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 SLEEPING R W 1 Specifies if the CPU is in Active, Sleep or DeepSleep
power mode:
- Active power mode: SLEEPING is '0'.
- Sleep power mode: SLEEPING is '1' and
SLEEPDEEP is '0'.
- DeepSleep power mode: SLEEPING is '1' and
SLEEPDEEP is '1'.
1 SLEEPDEEP R W 1 Specifies if the CPU is in Sleep or DeepSleep power
mode. See SLEEPING field.
4 PWR_DONE R W 1 After a PWR_MODE change this flag indicates if the
new power mode has taken effect or not.
Note: this flag can also change as a result of a change
in debug power up req
703
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers