Infineon TRAVEO T2G - 14.2.14 FLASHC_CM0_CA_STATUS2

Technical Reference Manual 002-29852 Rev. *B
14.2.14 FLASHC_CM0_CA_STATUS2
Description:
CM0+ cache status 2
Address:
0x40240448
Offset:
0x448
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:6] LRU [5:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:5 LRU R W Undefined Six bit LRU representation of the cache set specified
by CM0_CA_CTL.SET_ADDR. The encoding of the
field is as follows ('X_LRU_Y' indicates that way X is
Less Recently Used than way Y):
Bit 5: 0_LRU_1: way 0 less recently used than way 1.
Bit 4: 0_LRU_2.
Bit 3: 0_LRU_3.
Bit 2: 1_LRU_2.
Bit 1: 1_LRU_3.
Bit 0: 2_LRU_3.
951
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers