Infineon TRAVEO T2G - 28.2 GRP 1; 28.2.1 CNT 0; 28.2.2 CNT 1

Technical Reference Manual 002-29852 Rev. *B
Register Name Address Permission Description
TCPWM0_GRP0_CNT62_CC1
0x40381F18 FULL Counter compare/capture 1 register
TCPWM0_GRP0_CNT62_CC1_BUFF
0x40381F1C FULL Counter buffered compare/capture 1 register
TCPWM0_GRP0_CNT62_PERIOD
0x40381F20 FULL Counter period register
TCPWM0_GRP0_CNT62_PERIOD_BUFF
0x40381F24 FULL Counter buffered period register
TCPWM0_GRP0_CNT62_DT
0x40381F30 FULL Counter PWM dead time register
Note:DT_LINE_OUT_H DT_LINE_COMPL_OUT are not
available for this register
TCPWM0_GRP0_CNT62_TR_CMD
0x40381F40 FULL Counter trigger command register
TCPWM0_GRP0_CNT62_TR_IN_SEL0
0x40381F44 FULL Counter input trigger selection register 0
TCPWM0_GRP0_CNT62_TR_IN_SEL1
0x40381F48 FULL Counter input trigger selection register 1
TCPWM0_GRP0_CNT62_TR_IN_EDGE_SEL
0x40381F4C FULL Counter input trigger edge selection register
TCPWM0_GRP0_CNT62_TR_PWM_CTRL
0x40381F50 FULL Counter trigger PWM control register
TCPWM0_GRP0_CNT62_TR_OUT_SEL
0x40381F54 FULL Counter output trigger selection register
TCPWM0_GRP0_CNT62_INTR
0x40381F70 FULL Interrupt request register
TCPWM0_GRP0_CNT62_INTR_SET
0x40381F74 FULL Interrupt set request register
TCPWM0_GRP0_CNT62_INTR_MASK
0x40381F78 FULL Interrupt mask register
TCPWM0_GRP0_CNT62_INTR_MASKED
0x40381F7C FULL Interrupt masked request register
28.2 GRP 1
28.2.1 CNT 0
Register Name Address Permission Description
TCPWM0_GRP1_CNT0_CTRL
0x40388000 FULL Counter control register
TCPWM0_GRP1_CNT0_STATUS
0x40388004 FULL Counter status register
TCPWM0_GRP1_CNT0_COUNTER
0x40388008 FULL Counter count register
TCPWM0_GRP1_CNT0_CC0
0x40388010 FULL Counter compare/capture 0 register
TCPWM0_GRP1_CNT0_CC0_BUFF
0x40388014 FULL Counter buffered compare/capture 0 register
TCPWM0_GRP1_CNT0_CC1
0x40388018 FULL Counter compare/capture 1 register
TCPWM0_GRP1_CNT0_CC1_BUFF
0x4038801C FULL Counter buffered compare/capture 1 register
TCPWM0_GRP1_CNT0_PERIOD
0x40388020 FULL Counter period register
TCPWM0_GRP1_CNT0_PERIOD_BUFF
0x40388024 FULL Counter buffered period register
TCPWM0_GRP1_CNT0_LINE_SEL
0x40388028 FULL Counter line selection register
TCPWM0_GRP1_CNT0_LINE_SEL_BUFF
0x4038802C FULL Counter buffered line selection register
TCPWM0_GRP1_CNT0_DT
0x40388030 FULL Counter PWM dead time register
TCPWM0_GRP1_CNT0_TR_CMD
0x40388040 FULL Counter trigger command register
TCPWM0_GRP1_CNT0_TR_IN_SEL0
0x40388044 FULL Counter input trigger selection register 0
TCPWM0_GRP1_CNT0_TR_IN_SEL1
0x40388048 FULL Counter input trigger selection register 1
TCPWM0_GRP1_CNT0_TR_IN_EDGE_SEL
0x4038804C FULL Counter input trigger edge selection register
TCPWM0_GRP1_CNT0_TR_PWM_CTRL
0x40388050 FULL Counter trigger PWM control register
TCPWM0_GRP1_CNT0_TR_OUT_SEL
0x40388054 FULL Counter output trigger selection register
TCPWM0_GRP1_CNT0_INTR
0x40388070 FULL Interrupt request register
TCPWM0_GRP1_CNT0_INTR_SET
0x40388074 FULL Interrupt set request register
TCPWM0_GRP1_CNT0_INTR_MASK
0x40388078 FULL Interrupt mask register
TCPWM0_GRP1_CNT0_INTR_MASKED
0x4038807C FULL Interrupt masked request register
28.2.2 CNT 1
Register Name Address Permission Description
TCPWM0_GRP1_CNT1_CTRL
0x40388080 FULL Counter control register
TCPWM0_GRP1_CNT1_STATUS
0x40388084 FULL Counter status register
TCPWM0_GRP1_CNT1_COUNTER
0x40388088 FULL Counter count register
TCPWM0_GRP1_CNT1_CC0
0x40388090 FULL Counter compare/capture 0 register
TCPWM0_GRP1_CNT1_CC0_BUFF
0x40388094 FULL Counter buffered compare/capture 0 register
TCPWM0_GRP1_CNT1_CC1
0x40388098 FULL Counter compare/capture 1 register
TCPWM0_GRP1_CNT1_CC1_BUFF
0x4038809C FULL Counter buffered compare/capture 1 register
TCPWM0_GRP1_CNT1_PERIOD
0x403880A0 FULL Counter period register
TCPWM0_GRP1_CNT1_PERIOD_BUFF
0x403880A4 FULL Counter buffered period register
TCPWM0_GRP1_CNT1_LINE_SEL
0x403880A8 FULL Counter line selection register
TCPWM0_GRP1_CNT1_LINE_SEL_BUFF
0x403880AC FULL Counter buffered line selection register
TCPWM0_GRP1_CNT1_DT
0x403880B0 FULL Counter PWM dead time register
TCPWM0_GRP1_CNT1_TR_CMD
0x403880C0 FULL Counter trigger command register
TCPWM0_GRP1_CNT1_TR_IN_SEL0
0x403880C4 FULL Counter input trigger selection register 0
TCPWM0_GRP1_CNT1_TR_IN_SEL1
0x403880C8 FULL Counter input trigger selection register 1
TCPWM0_GRP1_CNT1_TR_IN_EDGE_SEL
0x403880CC FULL Counter input trigger edge selection register
1780
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers