Infineon TRAVEO T2G - 2.3.9.6.44 CANFD_CH_TXEFC

Technical Reference Manual 002-29852 Rev. *B
2.3.9.6.44 CANFD_CH_TXEFC
Description:
Tx Event FIFO Configuration
Address:
0x405200F0
Offset:
0xF0
Retention:
Retained
IsDeepSleep:
No
Comment:
Protected Write.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [1:0]
Bits 15 14 13 12 11 10 9 8
Name EFSA [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:22] EFS [21:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:30] EFWM [29:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
2:15 EFSA RW R 0 Event FIFO Start Address
Start address of Tx Event FIFO in Message RAM (32-
bit word address, see Figure 2).
16:21 EFS RW R 0 Event FIFO Size
0= Tx Event FIFO disabled
1-32= Number of Tx Event FIFO elements
32= Values greater than 32 are interpreted as 32
The Tx Event FIFO elements are indexed from 0 to
EFS-1
24:29 EFWM RW R 0 Event FIFO Watermark
0= Watermark interrupt disabled
1-32= Level for Tx Event FIFO watermark interrupt
(IR.TEFW)
32= Watermark interrupt disabled
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2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers