Infineon TRAVEO T2G - 7.5 Register Details; 7.5.1 CXPI_ERROR_CTL

Technical Reference Manual 002-29852 Rev. *B
7.5 Register Details
7.5.1 CXPI_ERROR_CTL
Description:
Error control
Address:
0x40510000
Offset:
0x0
Retention:
Retained
IsDeepSleep:
No
Comment:
This register supports error functionality: it enables HW injected channel transmitter errors.
The receiver should detect these errors and report these errors through activation of
corresponding interrupt causes.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:5] CH_IDX [4:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:21] TX_DATA
_LENGTH
_ERROR
[20:20]
TX_PID_PA
RITY
_ERROR
[19:19]
TX_CRC
_ERROR
[18:18]
None [17:16]
Bits 31 30 29 28 27 26 25 24
Name ENABLED
[31:31]
None [30:26] TX_DATA
_STOP
_ERROR
[25:25]
None
[24:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:4 CH_IDX RW R 0 Specifies the channel index of the channel to which
HW injected channel transmitter errors applies.
18 TX_CRC_ERROR RW R 0 The crc field is inverted.
At the receiver, this should result in
INTR.RX_CRC_ERROR activation.
19 TX_PID_PARITY
_ERROR
RW R 0 In cxpi mode, the PID parity bit P[1] is inverted from
!(ID[5] ^ ID[4] ^ ID[3] ^ ID[1]) to (ID[5] ^ ID[4] ^ ID[3] ^
ID[1]).
At the receiver, this should result in
INTR.RX_HEADER_PARITY_ERROR activation.
20 TX_DATA_LENGTH
_ERROR
RW R 0 The transmitter continues to send logical '0' (during
IFS) after CRC field is transmitted.
At the receiver, this should result in
INTR.RX_DATA_LENGTH_ERROR activation.
At the transmitter, this should result in
INTR.TX_DATA_LENGTH_ERROR activation.
25 TX_DATA_STOP
_ERROR
RW R 0 The data field STOP bits are inverted to '0'.
At the receiver, this should result in
INTR.RX_FRAME_ERROR activation.
At the transmitter, this should result in
INTR.TX_FRAME_ERROR activation.
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2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers