Infineon TRAVEO T2G - 19.5.1.3 PASS_SAR_PRECOND_CTL

Technical Reference Manual 002-29852 Rev. *B
19.5.1.3 PASS_SAR_PRECOND_CTL
Description:
Preconditioning control register.
Address:
0x40900010
Offset:
0x10
Retention:
Retained
IsDeepSleep:
No
Comment:
Precondition time value used when a channel enables preconditioning (PRECOND_MODE)
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:4] PRECOND_TIME [3:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:3 PRECOND_TIME RW R 0 Number ADC clock cycles that Preconditioning is done
before the sample window starts. If OVERLAP_EN=0
there will be 1 additional break before make cycle
between preconditioning and sampling.
Note that the minimum value is 1 (0 gives the same
result as 1).
1092
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers