Infineon TRAVEO T2G - 8.5.3.17 DMAC_CH_INTR_SET

Technical Reference Manual 002-29852 Rev. *B
8.5.3.17 DMAC_CH_INTR_SET
Description:
Interrupt set
Address:
0x402A1084
Offset:
0x84
Retention:
Not Retained
IsDeepSleep:
No
Comment:
When read, this register reflects the INTR register.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name DESCR
_BUS
_ERROR
[7:7]
ACTIVE
_CH
_DISABLED
[6:6]
CURR_PTR
_NULL [5:5]
DST
_MISAL
[4:4]
SRC
_MISAL
[3:3]
DST_BUS
_ERROR
[2:2]
SRC_BUS
_ERROR
[1:1]
COMPLETIO
N [0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits
Name SW HW Default or
Enum
Description
0 COMPLETION RW1S A 0 Write this field with '1' to set INTR.COMPLETION field
to '1' (a write of '0' has no effect).
1 SRC_BUS_ERROR RW1S A 0 Write this field with '1' to set INTR.SRC_BUS_ERROR
field to '1' (a write of '0' has no effect).
2 DST_BUS_ERROR RW1S A 0 Write this field with '1' to set INTR.DST_BUS_ERROR
field to '1' (a write of '0' has no effect).
3 SRC_MISAL RW1S A 0 Write this field with '1' to set INTR.SRC_MISAL field to
'1' (a write of '0' has no effect).
4 DST_MISAL RW1S A 0 Write this field with '1' to set INTR.DST_MISAL field to
'1' (a write of '0' has no effect).
5 CURR_PTR_NULL RW1S A 0 Write this field with '1' to set INTR.CURR_PTR_NULL
field to '1' (a write of '0' has no effect).
6 ACTIVE_CH_DISABLED RW1S A 0 Write this field with '1' to set
INTR.ACT_CH_DISABLED field to '1' (a write of '0' has
no effect).
7 DESCR_BUS_ERROR RW1S A 0 Write this field with '1' to set
INTR.DESCR_BUS_ERROR field to '1' (a write of '0'
has no effect).
824
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers