Infineon TRAVEO T2G - 3.8.3.26 CM0 P_SCS_DCRSR

Technical Reference Manual 002-29852 Rev. *B
3.8.3.26 CM0P_SCS_DCRSR
Description:
Debug Core Register Selector Register
Address:
0xE000EDF4
Offset:
0xDF4
Retention:
Retained
IsDeepSleep:
No
Comment:
With the DCRDR, see Debug Core Register Data Register, DCRDR on Arm TRM page C1-
337, the DCRSR provides debug access to the ARM core registers and special-purpose
registers. A write to DCRSR specifies the register to transfer, whether the transfer is a read or
a write, and starts the transfer. This register is only accessible in Debug state. When the
processor is in Debug state, the debugger must preserve the Exception number bits in the
IPSR, otherwise behavior is UNPREDICTABLE
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:5] REGSEL [4:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:17] REGWNR
[16:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:4 REGSEL RW R X Specifies the ARM core register or special-purpose
register to transfer.
R0 0 CPU R0
R1 1 CPU R1
R2 2 CPU R2
R3 3 CPU R3
R4 4 CPU R4
R5 5 CPU R5
R6 6 CPU R6
R7 7 CPU R7
R8 8 CPU R8
R9 9 CPU R9
R10 10 CPU R10
R11 11 CPU R11
R12 12 CPU R12
SP 13 Current Stack Pointer
LR 14 CPU LR
DBG_RA 15 DebugReturnAddress: the address of the first
instruction to be executed on exit from Debug state.
XPSR 16 xPSR
MSP 17 Main stack pointer, MSP.
PSP 18 Process stack pointer, PSP
C_P 20 [31:24]: CONTROL
[7:0]: PRIMASK.
16 REGWNR RW R X Specifies the type of access for the transfer.
READ 0 Read transfer
188
2022-04-18
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