Infineon TRAVEO T2G - 23.9.40 SCB_INTR_M_MASKED

Technical Reference Manual 002-29852 Rev. *B
23.9.40 SCB_INTR_M_MASKED
Description:
Master interrupt masked request
Address:
0x40600F0C
Offset:
0xF0C
Retention:
Not Retained
IsDeepSleep:
No
Comment:
When read, this register reflects a bitwise and between the interrupt request and mask
registers. This register allows SW to read the status of all mask enabled interrupt causes with
a single load operation, rather than two load operations: one for the interrupt causes and one
for the masks. This simplifies Firmware development. The associated interrupt is active ('1'),
when INTR_M_MASKED != 0.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:5] I2C_STOP
[4:4]
None [3:3] I2C_ACK
[2:2]
I2C_NACK
[1:1]
I2C_ARB_L
OST [0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:10] SPI_DONE
[9:9]
I2C_BUS_E
RROR [8:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 I2C_ARB_LOST R W 0 Logical and of corresponding request and mask bits.
1 I2C_NACK R W 0 Logical and of corresponding request and mask bits.
2 I2C_ACK R W 0 Logical and of corresponding request and mask bits.
4 I2C_STOP R W 0 Logical and of corresponding request and mask bits.
8 I2C_BUS_ERROR R W 0 Logical and of corresponding request and mask bits.
9 SPI_DONE R W 0 Logical and of corresponding request and mask bits.
1438
2022-04-18
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