Infineon TRAVEO T2G - 9.1.1.71 CH_STRUCT 70; 9.1.1.72 CH_STRUCT 71; 9.1.1.73 CH_STRUCT 72; 9.1.1.74 CH_STRUCT 73

Technical Reference Manual 002-29852 Rev. *B
Register Name Address Permission Description
DW0_CH_STRUCT69_TR_CMD
0x40289168 FULL Channel software trigger
9.1.1.71 CH_STRUCT 70
Register Name Address Permission Description
DW0_CH_STRUCT70_CH_CTL
0x40289180 FULL Channel control
DW0_CH_STRUCT70_CH_STATUS
0x40289184 FULL Channel status
DW0_CH_STRUCT70_CH_IDX
0x40289188 FULL Channel current indices
DW0_CH_STRUCT70_CH_CURR_PTR
0x4028918C FULL Channel current descriptor pointer
DW0_CH_STRUCT70_INTR
0x40289190 FULL Interrupt
DW0_CH_STRUCT70_INTR_SET
0x40289194 FULL Interrupt set
DW0_CH_STRUCT70_INTR_MASK
0x40289198 FULL Interrupt mask
DW0_CH_STRUCT70_INTR_MASKED
0x4028919C FULL Interrupt masked
DW0_CH_STRUCT70_SRAM_DATA0
0x402891A0 FULL SRAM data 0
DW0_CH_STRUCT70_SRAM_DATA1
0x402891A4 FULL SRAM data 1
DW0_CH_STRUCT70_TR_CMD
0x402891A8 FULL Channel software trigger
9.1.1.72 CH_STRUCT 71
Register Name Address Permission Description
DW0_CH_STRUCT71_CH_CTL
0x402891C0 FULL Channel control
DW0_CH_STRUCT71_CH_STATUS
0x402891C4 FULL Channel status
DW0_CH_STRUCT71_CH_IDX
0x402891C8 FULL Channel current indices
DW0_CH_STRUCT71_CH_CURR_PTR
0x402891CC FULL Channel current descriptor pointer
DW0_CH_STRUCT71_INTR
0x402891D0 FULL Interrupt
DW0_CH_STRUCT71_INTR_SET
0x402891D4 FULL Interrupt set
DW0_CH_STRUCT71_INTR_MASK
0x402891D8 FULL Interrupt mask
DW0_CH_STRUCT71_INTR_MASKED
0x402891DC FULL Interrupt masked
DW0_CH_STRUCT71_SRAM_DATA0
0x402891E0 FULL SRAM data 0
DW0_CH_STRUCT71_SRAM_DATA1
0x402891E4 FULL SRAM data 1
DW0_CH_STRUCT71_TR_CMD
0x402891E8 FULL Channel software trigger
9.1.1.73 CH_STRUCT 72
Register Name Address Permission Description
DW0_CH_STRUCT72_CH_CTL
0x40289200 FULL Channel control
DW0_CH_STRUCT72_CH_STATUS
0x40289204 FULL Channel status
DW0_CH_STRUCT72_CH_IDX
0x40289208 FULL Channel current indices
DW0_CH_STRUCT72_CH_CURR_PTR
0x4028920C FULL Channel current descriptor pointer
DW0_CH_STRUCT72_INTR
0x40289210 FULL Interrupt
DW0_CH_STRUCT72_INTR_SET
0x40289214 FULL Interrupt set
DW0_CH_STRUCT72_INTR_MASK
0x40289218 FULL Interrupt mask
DW0_CH_STRUCT72_INTR_MASKED
0x4028921C FULL Interrupt masked
DW0_CH_STRUCT72_SRAM_DATA0
0x40289220 FULL SRAM data 0
DW0_CH_STRUCT72_SRAM_DATA1
0x40289224 FULL SRAM data 1
DW0_CH_STRUCT72_TR_CMD
0x40289228 FULL Channel software trigger
9.1.1.74 CH_STRUCT 73
Register Name Address Permission Description
DW0_CH_STRUCT73_CH_CTL
0x40289240 FULL Channel control
DW0_CH_STRUCT73_CH_STATUS
0x40289244 FULL Channel status
DW0_CH_STRUCT73_CH_IDX
0x40289248 FULL Channel current indices
DW0_CH_STRUCT73_CH_CURR_PTR
0x4028924C FULL Channel current descriptor pointer
DW0_CH_STRUCT73_INTR
0x40289250 FULL Interrupt
DW0_CH_STRUCT73_INTR_SET
0x40289254 FULL Interrupt set
DW0_CH_STRUCT73_INTR_MASK
0x40289258 FULL Interrupt mask
DW0_CH_STRUCT73_INTR_MASKED
0x4028925C FULL Interrupt masked
DW0_CH_STRUCT73_SRAM_DATA0
0x40289260 FULL SRAM data 0
DW0_CH_STRUCT73_SRAM_DATA1
0x40289264 FULL SRAM data 1
DW0_CH_STRUCT73_TR_CMD
0x40289268 FULL Channel software trigger
9.1.1.75 CH_STRUCT 74
Register Name Address Permission Description
DW0_CH_STRUCT74_CH_CTL
0x40289280 FULL Channel control
DW0_CH_STRUCT74_CH_STATUS
0x40289284 FULL Channel status
DW0_CH_STRUCT74_CH_IDX
0x40289288 FULL Channel current indices
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