Technical Reference Manual 002-29852 Rev. *B
3.8.3 SCS
3.8.3.1 CM0P_SCS_SYST_CSR
Description:
SysTick Control & Status
Address:
0xE000E010
Offset:
0x10
Retention:
Retained
IsDeepSleep:
No
Comment:
Controls the SysTick counter and provides status data. The SysTick counter is functional in
the Active and Sleep power modes (and not functional in the DeepSleep, and Hibernate power
modes).
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:3] CLKSOURCE
[2:2]
TICKINT
[1:1]
ENABLE
[0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:17] COUNTFLAG
[16:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits
Name SW HW Default or
Enum
Description
0 ENABLE RW R 0 Indicates the enabled status of the SysTick counter:
'0': counter is disabled.
'1': counter is operating.
1 TICKINT RW R 0 Indicates whether counting to '0' causes the status of
the SysTick exception to change to pending:
'0': count to '0' does not affect the SysTick exception
status.
'1': count to '0' changes the SysTick exception status
to pending.
Changing the value of the counter to '0' by writing zero
to the SYST_CVR register to '0' never changes the
status of the SysTick exception.
2 CLKSOURCE RW R 0 Indicates the SysTick counter clock source:
'0': SysTick uses the low frequency clock. For this
mode to function, the low frequency clock should be
less than half the frequency of 'clk_sys'.
'1': SysTick uses the system/processor clock 'clk_sys'.
Note: Low frequency clock can be selected using
CPUSS_SYSTICK_CTL.CLOCK_SOURCE field.
16 COUNTFLAG R RW 0 Indicates whether the counter has counted to '0' since
the last read of this register:
'0': counter has not counted to '0'.
'1': counter has counted to '0'.
COUNTFLAG is set to '1' by a count transition from '1'
to '0'.
COUNTFLAG is cleared to '0' by a read of this register,
and by any write to the SYST_CVR register.
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers
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