Infineon TRAVEO T2G - 2.3.9.6.30 CANFD_CH_RXF1 C

Technical Reference Manual 002-29852 Rev. *B
2.3.9.6.30 CANFD_CH_RXF1C
Description:
Rx FIFO 1 Configuration
Address:
0x405200B0
Offset:
0xB0
Retention:
Retained
IsDeepSleep:
No
Comment:
Protected Write.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [1:0]
Bits 15 14 13 12 11 10 9 8
Name F1SA [15:8]
Bits 23 22 21 20 19 18 17 16
Name None
[23:23]
F1S [22:16]
Bits 31 30 29 28 27 26 25 24
Name F1OM
[31:31]
F1WM [30:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
2:15 F1SA RW R 0 Rx FIFO 1 Start Address
Start address of Rx FIFO 1 in Message RAM (32-bit
word address, see Figure 2).
16:22 F1S RW R 0 Rx FIFO 1 Size
0= No Rx FIFO 1
1-64= Number of Rx FIFO 1 elements
64= Values greater than 64 are interpreted as 64
The Rx FIFO 1 elements are indexed from 0 to F1S - 1
24:30 F1WM RW R 0 Rx FIFO 1 Watermark
0= Watermark interrupt disabled
1-64= Level for Rx FIFO 1 watermark interrupt
(IR.RF1W)
64= Watermark interrupt disabled
31 F1OM RW R 0 FIFO 1 Operation Mode
FIFO 1 can be operated in blocking or in overwrite
mode (see Section 3.4.2).
0= FIFO 1 blocking mode
1= FIFO 1 overwrite mode
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2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers