Infineon TRAVEO T2G - 5.1.30 CPUSS_RAM0_CTL0

Technical Reference Manual 002-29852 Rev. *B
5.1.30 CPUSS_RAM0_CTL0
Description:
RAM 0 control
Address:
0x40201300
Offset:
0x1300
Retention:
Retained
IsDeepSleep:
No
Comment:
This register is for the CPUSS system SRAM controller 0.
Default:
0x30001
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:2] SLOW_WS [1:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:10] FAST_WS [9:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:19] ECC_INJ_E
N [18:18]
ECC_AUTO
_
CORRECT
[17:17]
ECC_EN
[16:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits
Name SW HW Default or
Enum
Description
0:1 SLOW_WS RW R 1 Memory wait states for the slow clock domain
('clk_slow'). The number of wait states is expressed in
'clk_hf' clock domain cycles.
8:9 FAST_WS RW R 0 Memory wait states for the fast clock domain
('clk_fast'). The number of wait states is expressed in
'clk_hf' clock domain cycles.
16 ECC_EN RW R 1 Enable ECC checking:
'0': Disabled.
'1': Enabled.
17 ECC_AUTO_CORRECT RW R 1 HW ECC autocorrect functionality:
'0': Disabled.
'1': Enabled. HW automatically writes back SRAM with
corrected data when a recoverable ECC error is
detected.
18 ECC_INJ_EN RW R 0 Enable error injection for system SRAM 0.
When '1', the parity (ECC_CTL.PARITY) is used when
a full 32-bit write is done to the
ECC_CTL.WORD_ADDR word address of system
SRAM 0.
732
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers