Infineon TRAVEO T2G - 5.1.15 CPUSS_CM0_CTL

Technical Reference Manual 002-29852 Rev. *B
5.1.15 CPUSS_CM0_CTL
Description:
CM0+ control
Address:
0x40201000
Offset:
0x1000
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0xFA050002
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:2] ENABLED
[1:1]
SLV
_STALL
[0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name VECTKEYSTAT [23:16]
Bits 31 30 29 28 27 26 25 24
Name VECTKEYSTAT [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 SLV_STALL RW R 0 Processor debug access control:
'0': Access.
'1': Stall access.
This field is used to stall/delay debug accesses. This is
useful to protect execution of code that needs to be
protected from debug accesses.
1 ENABLED RW RW1S 1 Processor enable:
'0': Disabled. Processor clock is turned off and reset is
activated. After SW clears this field to '0', HW
automatically sets this field to '1'. This effectively
results in a CM0+ reset, followed by a CM0+ warm
boot.
'1': Enabled.
Note: The intent is that this bit is modified only through
an external probe or by the CM4 while the CM0+ is in
Sleep or DeepSleep power mode. If this field is cleared
to '0' by the CM0+ itself, it should be done under
controlled conditions (such that undesirable side
effects can be prevented).
Note: The CM0+ CPU has a AIRCR.SYSRESETREQ
register field that allows the CM0+ to reset the
complete device (ENABLED only disables/enables the
CM0+), resulting in a warm boot. This CPU register
field has similar 'built-in protection' as this CM0_CTL
register to prevent accidental system writes (the upper
16-bits of the register need to be written with a 0x05fa
key value; see CPU user manual for more details).
16:31 VECTKEYSTAT R 64005 Register key (to prevent accidental writes).
- Should be written with a 0x05fa key value for the
write to take effect.
- Always reads as 0xfa05.
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2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers