Infineon TRAVEO T2G - 4.13.3.3 CM4_FPB_COMP

Technical Reference Manual 002-29852 Rev. *B
4.13.3.3 CM4_FPB_COMP
Description:
FlashPatch Comparator register
Address:
0xE0002008
Offset:
0x8
Retention:
Retained
IsDeepSleep:
No
Comment:
The FP_COMPn register characteristics are:
Purpose:
Holds an address for comparison with addresses in the Code memory region, see The system
address map on page B3-648. The effect of a match depends on whether the comparator is
an instruction address comparator or a literal address comparator:
Instruction address comparators
Either:
- Defines an instruction address to remap to an address based on the address specified in the
FP_REMAP register.
- Defines a breakpoint address.
Literal address comparators
Defines a literal address to remap to an address based on the address specified in the
FP_REMAP register.
The FP_CTRL register determines which comparators are instruction address comparators
and which are literal address comparators. The version of the FPB unit determines the bit
assignment for the FP_COMP register. The FP_CTRL.REV field determines which version of
the FPB unit is attached. See FlashPatch Control Register, FP_CTRL on Arm TRM page C1-
816.
The FP_REMAP.RMPSPT field determines if the FPB unit supports Flash Patch. For more
information about address remapping see FlashPatch Remap register, FP_REMAP on page
C1-818.
If the FPB unit is configured for remap then FP_COMPn defines a 29-bit word-aligned
address.
If the FPB unit is configured for breakpoints, version 1 defines a 29-bit word-aligned address
and the breakpoint can be set on either or both half-words at this address. For version 2 FPB
units configured for breakpoints, FP_COMPn defines a 32-bit half-word aligned address.
Usage constraints: To enable a comparator, both the FP_CTRL.ENABLE bit and the required
FP_COMPn.ENABLE bit must be set to 1.
Configuration: Always implemented. see FlashPatch Control Register, FP_CTRL on Arm TRM
page C1-816 for information about the number of implemented FlashPatch comparator
registers.
Attributes: See Table C1-23 on Arm TRM page C1-816.
Default:
0x0
Bit-field Table
Bits
7 6 5 4 3 2 1 0
Name VALUE [7:0]
Bits 15 14 13 12 11 10 9 8
Name VALUE [15:8]
Bits 23 22 21 20 19 18 17 16
Name VALUE [23:16]
Bits 31 30 29 28 27 26 25 24
Name VALUE [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:31 VALUE RW R 0 See ARM documentation for details.
371
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers