Infineon TRAVEO T2G - 21.504.2.3 PERI_MS_PPU_FX_SL_ATT0

Technical Reference Manual 002-29852 Rev. *B
21.504.2.3 PERI_MS_PPU_FX_SL_ATT0
Description:
Slave attributes 0
Address:
0x40010810
Offset:
0x10
Retention:
Retained
IsDeepSleep:
No
Comment:
The access privileges for SL_ATT0, ..., SL_ATT3 are determined by MS_ATT0, ..., MS_ATT3.
Note that protection context '0' has unrestricted access: PC0_UR, ..., PC0_NS fields are fixed
to '1's. The other protection contexts have SW programmable fields.
Typically, the SL_ATT0, ..., SL_ATT3 registers are initialized by the boot process with
protection context '0'.
For 4 or less protection contexts (PC_NR <= 4), only SL_ATT0 is present. For 5 through 8
protection contexts, only SL_ATT0 and SL_ATT1 are present. For 9 through 12 or less
protection contexts, only SL_ATT0, SL_ATT1 and SL_ATT2 are present. For 13 through 16
protection contexts, SL_ATT0, SL_ATT1, SL_ATT2 and SL_ATT3 are all present. If the
number of protection contexts is not a multiple of 4, the 'missing' protection contexts in a
register have no associated access fields (and the field positions read as '0').
Default:
0x1F1F1F1F
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:5] PC0_NS
[4:4]
PC0_PW
[3:3]
PC0_PR
[2:2]
PC0_UW
[1:1]
PC0_UR
[0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:13] PC1_NS
[12:12]
PC1_PW
[11:11]
PC1_PR
[10:10]
PC1_UW
[9:9]
PC1_UR
[8:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:21] PC2_NS
[20:20]
PC2_PW
[19:19]
PC2_PR
[18:18]
PC2_UW
[17:17]
PC2_UR
[16:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:29] PC3_NS
[28:28]
PC3_PW
[27:27]
PC3_PR
[26:26]
PC3_UW
[25:25]
PC3_UR
[24:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 PC0_UR R R 1 Protection context 0, user read enable:
'0': Disabled (user, read accesses are NOT allowed).
'1': Enabled (user, read accesses are allowed).
1 PC0_UW R R 1 Protection context 0, user write enable:
'0': Disabled (user, write accesses are NOT allowed).
'1': Enabled (user, write accesses are allowed).
2 PC0_PR R R 1 Protection context 0, privileged read enable:
'0': Disabled (privileged, read accesses are NOT
allowed).
'1': Enabled (privileged, read accesses are allowed).
3 PC0_PW R R 1 Protection context 0, privileged write enable:
'0': Disabled (privileged, write accesses are NOT
allowed).
'1': Enabled (privileged, write accesses are allowed).
1298
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers