Technical Reference Manual 002-29852 Rev. *B
2.3.9.6.9 CANFD_CH_TSCV
Description:
Timestamp Counter Value
Address:
0x40520024
Offset:
0x24
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name TSC [7:0]
Bits 15 14 13 12 11 10 9 8
Name TSC [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:15 TSC RW R 0 Timestamp Counter, not used for M_TTCAN
The internal/external Timestamp Counter value is
captured on start of frame (both Rx and Tx).
When TSCC.TSS = '01', the Timestamp Counter is
incremented in multiples of CAN bit times
[1...16] depending on the configuration of TSCC.TCP.
A wrap around sets interrupt flag IR.TSW.
Write access resets the counter to zero. When
TSCC.TSS = '10', TSC reflects the external
Timestamp Counter value. A write access has no
impact.
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers