Infineon TRAVEO T2G - 17.17.2 INTR_STRUCT; 17.17.2.1 IPC_INTR_STRUCT_INTR

Technical Reference Manual 002-29852 Rev. *B
17.17.2 INTR_STRUCT
17.17.2.1 IPC_INTR_STRUCT_INTR
Description:
Interrupt
Address:
0x40221000
Offset:
0x0
Retention:
Not Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name RELEASE [7:0]
Bits 15 14 13 12 11 10 9 8
Name RELEASE [15:8]
Bits 23 22 21 20 19 18 17 16
Name NOTIFY [23:16]
Bits 31 30 29 28 27 26 25 24
Name NOTIFY [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:15 RELEASE RW1C RW1S 0 These interrupt cause fields are activated (HW sets the
field to '1') when a IPC release event is detected. One
bit field for each master. SW writes a '1' to these field
to clear the interrupt cause.
16:31 NOTIFY RW1C RW1S 0 These interrupt cause fields are activated (HW sets the
field to '1') when a IPC notification event is detected.
One bit field for each master. SW writes a '1' to these
field to clear the interrupt cause.
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2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers