Technical Reference Manual 002-29852 Rev. *B
Register Name Address Permission Description
PERI_MS_PPU_FX48_SL_ADDR
0x40011400 FULL Slave region, base address
PERI_MS_PPU_FX48_SL_SIZE
0x40011404 FULL Slave region, size
PERI_MS_PPU_FX48_SL_ATT0
0x40011410 FULL Slave attributes 0
PERI_MS_PPU_FX48_SL_ATT1
0x40011414 FULL Slave attributes 1
PERI_MS_PPU_FX48_SL_ATT2
0x40011418 FULL Slave attributes 2
PERI_MS_PPU_FX48_SL_ATT3
0x4001141C FULL Slave attributes 3
PERI_MS_PPU_FX48_MS_ADDR
0x40011420 FULL Master region, base address
PERI_MS_PPU_FX48_MS_SIZE
0x40011424 FULL Master region, size
PERI_MS_PPU_FX48_MS_ATT0
0x40011430 FULL Master attributes 0
PERI_MS_PPU_FX48_MS_ATT1
0x40011434 FULL Master attributes 1
PERI_MS_PPU_FX48_MS_ATT2
0x40011438 FULL Master attributes 2
PERI_MS_PPU_FX48_MS_ATT3
0x4001143C FULL Master attributes 3
21.66 PPU_FX 49
Register Name Address Permission Description
PERI_MS_PPU_FX49_SL_ADDR
0x40011440 FULL Slave region, base address
PERI_MS_PPU_FX49_SL_SIZE
0x40011444 FULL Slave region, size
PERI_MS_PPU_FX49_SL_ATT0
0x40011450 FULL Slave attributes 0
PERI_MS_PPU_FX49_SL_ATT1
0x40011454 FULL Slave attributes 1
PERI_MS_PPU_FX49_SL_ATT2
0x40011458 FULL Slave attributes 2
PERI_MS_PPU_FX49_SL_ATT3
0x4001145C FULL Slave attributes 3
PERI_MS_PPU_FX49_MS_ADDR
0x40011460 FULL Master region, base address
PERI_MS_PPU_FX49_MS_SIZE
0x40011464 FULL Master region, size
PERI_MS_PPU_FX49_MS_ATT0
0x40011470 FULL Master attributes 0
PERI_MS_PPU_FX49_MS_ATT1
0x40011474 FULL Master attributes 1
PERI_MS_PPU_FX49_MS_ATT2
0x40011478 FULL Master attributes 2
PERI_MS_PPU_FX49_MS_ATT3
0x4001147C FULL Master attributes 3
21.67 PPU_FX 50
Register Name Address Permission Description
PERI_MS_PPU_FX50_SL_ADDR
0x40011480 FULL Slave region, base address
PERI_MS_PPU_FX50_SL_SIZE
0x40011484 FULL Slave region, size
PERI_MS_PPU_FX50_SL_ATT0
0x40011490 FULL Slave attributes 0
PERI_MS_PPU_FX50_SL_ATT1
0x40011494 FULL Slave attributes 1
PERI_MS_PPU_FX50_SL_ATT2
0x40011498 FULL Slave attributes 2
PERI_MS_PPU_FX50_SL_ATT3
0x4001149C FULL Slave attributes 3
PERI_MS_PPU_FX50_MS_ADDR
0x400114A0 FULL Master region, base address
PERI_MS_PPU_FX50_MS_SIZE
0x400114A4 FULL Master region, size
PERI_MS_PPU_FX50_MS_ATT0
0x400114B0 FULL Master attributes 0
PERI_MS_PPU_FX50_MS_ATT1
0x400114B4 FULL Master attributes 1
PERI_MS_PPU_FX50_MS_ATT2
0x400114B8 FULL Master attributes 2
PERI_MS_PPU_FX50_MS_ATT3
0x400114BC FULL Master attributes 3
21.68 PPU_FX 51
Register Name Address Permission Description
PERI_MS_PPU_FX51_SL_ADDR
0x400114C0 FULL Slave region, base address
PERI_MS_PPU_FX51_SL_SIZE
0x400114C4 FULL Slave region, size
PERI_MS_PPU_FX51_SL_ATT0
0x400114D0 FULL Slave attributes 0
PERI_MS_PPU_FX51_SL_ATT1
0x400114D4 FULL Slave attributes 1
PERI_MS_PPU_FX51_SL_ATT2
0x400114D8 FULL Slave attributes 2
PERI_MS_PPU_FX51_SL_ATT3
0x400114DC FULL Slave attributes 3
PERI_MS_PPU_FX51_MS_ADDR
0x400114E0 FULL Master region, base address
PERI_MS_PPU_FX51_MS_SIZE
0x400114E4 FULL Master region, size
PERI_MS_PPU_FX51_MS_ATT0
0x400114F0 FULL Master attributes 0
PERI_MS_PPU_FX51_MS_ATT1
0x400114F4 FULL Master attributes 1
PERI_MS_PPU_FX51_MS_ATT2
0x400114F8 FULL Master attributes 2
PERI_MS_PPU_FX51_MS_ATT3
0x400114FC FULL Master attributes 3
21.69 PPU_FX 52
Register Name Address Permission Description
PERI_MS_PPU_FX52_SL_ADDR
0x40011500 FULL Slave region, base address
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers