Technical Reference Manual 002-29852 Rev. *B
Register Name Address Permission Description
TCPWM0_GRP0_CNT1_INTR
0x403800F0 FULL Interrupt request register
TCPWM0_GRP0_CNT1_INTR_SET
0x403800F4 FULL Interrupt set request register
TCPWM0_GRP0_CNT1_INTR_MASK
0x403800F8 FULL Interrupt mask register
TCPWM0_GRP0_CNT1_INTR_MASKED
0x403800FC FULL Interrupt masked request register
28.1.3 CNT 2
Register Name Address Permission Description
TCPWM0_GRP0_CNT2_CTRL
0x40380100 FULL Counter control register
Note:AUTO_RELOAD_LINE_SEL CC0_MATCH_UP_EN
CC0_MATCH_DOWN_EN CC1_MATCH_UP_EN
CC1_MATCH_DOWN_EN are not available for this
register
TCPWM0_GRP0_CNT2_STATUS
0x40380104 FULL Counter status register
Note:DT_CNT_H is not available for this register
TCPWM0_GRP0_CNT2_COUNTER
0x40380108 FULL Counter count register
TCPWM0_GRP0_CNT2_CC0
0x40380110 FULL Counter compare/capture 0 register
TCPWM0_GRP0_CNT2_CC0_BUFF
0x40380114 FULL Counter buffered compare/capture 0 register
TCPWM0_GRP0_CNT2_CC1
0x40380118 FULL Counter compare/capture 1 register
TCPWM0_GRP0_CNT2_CC1_BUFF
0x4038011C FULL Counter buffered compare/capture 1 register
TCPWM0_GRP0_CNT2_PERIOD
0x40380120 FULL Counter period register
TCPWM0_GRP0_CNT2_PERIOD_BUFF
0x40380124 FULL Counter buffered period register
TCPWM0_GRP0_CNT2_DT
0x40380130 FULL Counter PWM dead time register
Note:DT_LINE_OUT_H DT_LINE_COMPL_OUT are not
available for this register
TCPWM0_GRP0_CNT2_TR_CMD
0x40380140 FULL Counter trigger command register
TCPWM0_GRP0_CNT2_TR_IN_SEL0
0x40380144 FULL Counter input trigger selection register 0
TCPWM0_GRP0_CNT2_TR_IN_SEL1
0x40380148 FULL Counter input trigger selection register 1
TCPWM0_GRP0_CNT2_TR_IN_EDGE_SEL
0x4038014C FULL Counter input trigger edge selection register
TCPWM0_GRP0_CNT2_TR_PWM_CTRL
0x40380150 FULL Counter trigger PWM control register
TCPWM0_GRP0_CNT2_TR_OUT_SEL
0x40380154 FULL Counter output trigger selection register
TCPWM0_GRP0_CNT2_INTR
0x40380170 FULL Interrupt request register
TCPWM0_GRP0_CNT2_INTR_SET
0x40380174 FULL Interrupt set request register
TCPWM0_GRP0_CNT2_INTR_MASK
0x40380178 FULL Interrupt mask register
TCPWM0_GRP0_CNT2_INTR_MASKED
0x4038017C FULL Interrupt masked request register
28.1.4 CNT 3
Register Name Address Permission Description
TCPWM0_GRP0_CNT3_CTRL
0x40380180 FULL Counter control register
Note:AUTO_RELOAD_LINE_SEL CC0_MATCH_UP_EN
CC0_MATCH_DOWN_EN CC1_MATCH_UP_EN
CC1_MATCH_DOWN_EN are not available for this
register
TCPWM0_GRP0_CNT3_STATUS
0x40380184 FULL Counter status register
Note:DT_CNT_H is not available for this register
TCPWM0_GRP0_CNT3_COUNTER
0x40380188 FULL Counter count register
TCPWM0_GRP0_CNT3_CC0
0x40380190 FULL Counter compare/capture 0 register
TCPWM0_GRP0_CNT3_CC0_BUFF
0x40380194 FULL Counter buffered compare/capture 0 register
TCPWM0_GRP0_CNT3_CC1
0x40380198 FULL Counter compare/capture 1 register
TCPWM0_GRP0_CNT3_CC1_BUFF
0x4038019C FULL Counter buffered compare/capture 1 register
TCPWM0_GRP0_CNT3_PERIOD
0x403801A0 FULL Counter period register
TCPWM0_GRP0_CNT3_PERIOD_BUFF
0x403801A4 FULL Counter buffered period register
TCPWM0_GRP0_CNT3_DT
0x403801B0 FULL Counter PWM dead time register
Note:DT_LINE_OUT_H DT_LINE_COMPL_OUT are not
available for this register
TCPWM0_GRP0_CNT3_TR_CMD
0x403801C0 FULL Counter trigger command register
TCPWM0_GRP0_CNT3_TR_IN_SEL0
0x403801C4 FULL Counter input trigger selection register 0
TCPWM0_GRP0_CNT3_TR_IN_SEL1
0x403801C8 FULL Counter input trigger selection register 1
TCPWM0_GRP0_CNT3_TR_IN_EDGE_SEL
0x403801CC FULL Counter input trigger edge selection register
TCPWM0_GRP0_CNT3_TR_PWM_CTRL
0x403801D0 FULL Counter trigger PWM control register
TCPWM0_GRP0_CNT3_TR_OUT_SEL
0x403801D4 FULL Counter output trigger selection register
TCPWM0_GRP0_CNT3_INTR
0x403801F0 FULL Interrupt request register
TCPWM0_GRP0_CNT3_INTR_SET
0x403801F4 FULL Interrupt set request register
TCPWM0_GRP0_CNT3_INTR_MASK
0x403801F8 FULL Interrupt mask register
TCPWM0_GRP0_CNT3_INTR_MASKED
0x403801FC FULL Interrupt masked request register
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers
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