Technical Reference Manual 002-29852 Rev. *B
5.1.38 CPUSS_ECC_CTL
Description:
ECC control
Address:
0x402013C8
Offset:
0x13C8
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name WORD_ADDR [7:0]
Bits 15 14 13 12 11 10 9 8
Name WORD_ADDR [15:8]
Bits 23 22 21 20 19 18 17 16
Name WORD_ADDR [23:16]
Bits 31 30 29 28 27 26 25 24
Name PARITY [31:25] WORD
_ADDR
[24:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:24 WORD_ADDR RW R 0 Specifies the word address where an error will be
injected.
- On a write transfer to this SRAM address and when
the corresponding
RAM0/RAM1/RAM2_CTL0.ECC_INJ_EN bit is '1', the
parity (PARITY) is injected.
This field needs to be written with the offset address
within the memory, divided by 4.
For example, if the RAM1 start address is
0x08010000, and an error is to be injected to address
0x08010040, then this field needs to configured to
0x000010.
25:31 PARITY RW R 0 ECC parity to use for ECC error injection at address
WORD_ADDR.
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers
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