Infineon TRAVEO T2G - 8.5.3.7 DMAC_CH_DESCR_STATUS

Technical Reference Manual 002-29852 Rev. *B
8.5.3.7 DMAC_CH_DESCR_STATUS
Description:
Channel descriptor status
Address:
0x402A1040
Offset:
0x40
Retention:
Not Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name VALID
[31:31]
None [30:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
31 VALID R W 0 Indicates whether the descriptor information present in
DESCR_CTL, DESCR_SRC, DESCR_DST,
DESCR_X_SIZE, DESCR_X_INCR, DESCR_Y_SIZE,
DESCR_Y_INCR, DESCR_NEXT status registers is
valid or not.
811
2022-04-18
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