Infineon TRAVEO T2G - 17.17.2.2 IPC_INTR_STRUCT_INTR_SET

Technical Reference Manual 002-29852 Rev. *B
17.17.2.2 IPC_INTR_STRUCT_INTR_SET
Description:
Interrupt set
Address:
0x40221004
Offset:
0x4
Retention:
Not Retained
IsDeepSleep:
No
Comment:
When read, this register reflects the INTR register. For debug purposes, SW can write a '1' to
activate a specific interrupt cause (this allows for debug of the SW ISR, without relying on HW
to activate the interrupt cause).
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name RELEASE [7:0]
Bits 15 14 13 12 11 10 9 8
Name RELEASE [15:8]
Bits 23 22 21 20 19 18 17 16
Name NOTIFY [23:16]
Bits 31 30 29 28 27 26 25 24
Name NOTIFY [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:15 RELEASE RW1S A 0 SW writes a '1' to this field to set the corresponding
field in the INTR register.
16:31 NOTIFY RW1S A 0 SW writes a '1' to this field to set the corresponding
field in the INTR register.
1034
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers