Infineon TRAVEO T2G - 1.1.14 BACKUP_INTR_MASKED

Technical Reference Manual 002-29852 Rev. *B
1.1.14 BACKUP_INTR_MASKED
Description:
Interrupt masked request register
Address:
0x40270038
Offset:
0x38
Retention:
Retained
IsDeepSleep:
No
Comment:
These bits are in vddbak domain. When read, this register reflects a bitwise and between the
interrupt request and mask registers.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:3] CENTURY
[2:2]
ALARM2
[1:1]
ALARM1
[0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 ALARM1 R RW 0 Logical and of corresponding request and mask bits.
1 ALARM2 R RW 0 Logical and of corresponding request and mask bits.
2 CENTURY R RW 0 Logical and of corresponding request and mask bits.
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2022-04-18
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