Infineon TRAVEO T2G - 20.30.4 PERI_CLOCK_CTL

Technical Reference Manual 002-29852 Rev. *B
20.30.4 PERI_CLOCK_CTL
Description:
Clock control
Address:
0x40000C00
Offset:
0xC00
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x3FF
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name DIV_SEL [7:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:10] TYPE_SEL [9:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:7 DIV_SEL RW R 255 Specifies one of the dividers of the divider type
specified by TYPE_SEL.
If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset
value), no divider is specified and no clock control
signal(s) are generated.
When transitioning a clock between two out-of-phase
dividers, spurious clock control signals may be
generated for one 'clk_peri' cycle during this transition.
These clock control signals may cause a single clock
period that is smaller than any of the two divider
periods. To prevent these spurious clock signals, the
clock multiplexer can be disconnected (DIV_SEL is
'255' and TYPE_SEL is '3') for a transition time that is
larger than the smaller of the two divider periods.
8:9 TYPE_SEL RW R 3 Specifies divider type:
0: 8.0 (integer) clock dividers.
1: 16.0 (integer) clock dividers.
2: 16.5 (fractional) clock dividers.
3: 24.5 (fractional) clock dividers.
1145
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers