Infineon TRAVEO T2G - Page 1144

Technical Reference Manual 002-29852 Rev. *B
Bits Name SW HW Default or
Enum
Description
24:25 PA_TYPE_SEL RW R 3 Specifies the divider type of the divider to which phase
alignment is performed for the clock enable command:
0: 8.0 (integer) clock dividers.
1: 16.0 (integer) clock dividers.
2: 16.5 (fractional) clock dividers.
3: 24.5 (fractional) clock dividers.
30 DISABLE RW RW1C 0 Clock divider disable command (mutually exclusive
with ENABLE). SW sets this field to '1' and HW sets
this field to '0'.
The DIV_SEL and TYPE_SEL fields specify which
divider is to be disabled.
The HW sets the DISABLE field to '0' immediately and
the HW sets the DIV_XXX_CTL.EN field of the divider
to '0' immediately.
31 ENABLE RW RW1C 0 Clock divider enable command (mutually exclusive
with DISABLE). Typically, SW sets this field to '1' to
enable a divider and HW sets this field to '0' to indicate
that divider enabling has completed. When a divider is
enabled, its integer and fractional (if present) counters
are initialized to '0'. If a divider is to be re-enabled
using different integer and fractional divider values, the
SW should follow these steps:
0: Disable the divider using the DIV_CMD.DISABLE
field.
1: Configure the divider's DIV_XXX_CTL register.
2: Enable the divider using the DIV_CMD_ENABLE
field.
The DIV_SEL and TYPE_SEL fields specify which
divider is to be enabled. The enabled divider may be
phase aligned to either 'clk_peri' (typical usage) or to
ANY enabled divider.
The PA_DIV_SEL and PA_TYPE_SEL fields specify
the reference divider.
The HW sets the ENABLE field to '0' when the
enabling is performed and the HW set the
DIV_XXX_CTL.EN field of the divider to '1' when the
enabling is performed. Note that enabling with phase
alignment to a low frequency divider takes time. E.g.
To align to a divider that generates a clock of
'clk_peri'/n (with n being the integer divider value
INT_DIV+1), up to n cycles may be required to perform
alignment. Phase alignment to 'clk_peri' takes affect
immediately. SW can set this field to '0' during phase
alignment to abort the enabling process.
1144
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers