Technical Reference Manual 002-29852 Rev. *B
21.504.1.12 PERI_MS_PPU_PR_MS_ATT3
Description:
Master attributes 3
Address:
0x4001003C
Offset:
0x3C
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x1F1F1F1F
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:5] PC12_NS
[4:4]
PC12_PW
[3:3]
PC12_PR
[2:2]
PC12_UW
[1:1]
PC12_UR
[0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:13] PC13_NS
[12:12]
PC13_PW
[11:11]
PC13_PR
[10:10]
PC13_UW
[9:9]
PC13_UR
[8:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:21] PC14_NS
[20:20]
PC14_PW
[19:19]
PC14_PR
[18:18]
PC14_UW
[17:17]
PC14_UR
[16:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:29] PC15_NS
[28:28]
PC15_PW
[27:27]
PC15_PR
[26:26]
PC15_UW
[25:25]
PC15_UR
[24:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 PC12_UR R R 1 Protection context 12, user read enable.
1 PC12_UW RW R 1 Protection context 12, user write enable.
2 PC12_PR R R 1 Protection context 12, privileged read enable.
3 PC12_PW RW R 1 Protection context 12, privileged write enable.
4 PC12_NS RW R 1 Protection context 12, non-secure.
8 PC13_UR R R 1 Protection context 13, user read enable.
9 PC13_UW RW R 1 Protection context 13, user write enable.
10 PC13_PR R R 1 Protection context 13, privileged read enable.
11 PC13_PW RW R 1 Protection context 13, privileged write enable.
12 PC13_NS RW R 1 Protection context 13, non-secure.
16 PC14_UR R R 1 Protection context 14, user read enable.
17 PC14_UW RW R 1 Protection context 14, user write enable.
18 PC14_PR R R 1 Protection context 14, privileged read enable.
19 PC14_PW RW R 1 Protection context 14, privileged write enable.
20 PC14_NS RW R 1 Protection context 14, non-secure.
24 PC15_UR R R 1 Protection context 15, user read enable.
25 PC15_UW RW R 1 Protection context 15, user write enable.
26 PC15_PR R R 1 Protection context 15, privileged read enable.
27 PC15_PW RW R 1 Protection context 15, privileged write enable.
28 PC15_NS RW R 1 Protection context 15, non-secure.
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers