Infineon TRAVEO T2G - 26.8.50.10 MCWDT_INTR_MASKED

Technical Reference Manual 002-29852 Rev. *B
26.8.50.10 MCWDT_INTR_MASKED
Description:
MCWDT Interrupt Masked Register
Address:
0x402680AC
Offset:
0xAC
Retention:
Retained
IsDeepSleep:
No
Comment:
Bitwise AND between the interrupt request and mask registers so firmware can read the status
of all mask enabled interrupt causes with a single load operation. Each available MCWDT has
a copy of this register.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:3] CTR2_INT
[2:2]
CTR1_INT
[1:1]
CTR0_INT
[0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 CTR0_INT R RW 0 Logical and of corresponding request and mask bits.
1 CTR1_INT R RW 0 Logical and of corresponding request and mask bits.
2 CTR2_INT R RW 0 Logical and of corresponding request and mask bits.
1714
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers