Infineon TRAVEO T2G - 8.5.3.16 DMAC_CH_INTR

Technical Reference Manual 002-29852 Rev. *B
8.5.3.16 DMAC_CH_INTR
Description:
Interrupt
Address:
0x402A1080
Offset:
0x80
Retention:
Not Retained
IsDeepSleep:
No
Comment:
The register fields are not retained. This is to ensure that they come up as '0' after coming out
of DeepSleep system power mode.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name DESCR
_BUS
_ERROR
[7:7]
ACTIVE
_CH
_DISABLED
[6:6]
CURR_PTR
_NULL [5:5]
DST
_MISAL
[4:4]
SRC
_MISAL
[3:3]
DST_BUS
_ERROR
[2:2]
SRC_BUS
_ERROR
[1:1]
COMPLETIO
N [0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits
Name SW HW Default or
Enum
Description
0 COMPLETION RW1C RW1S 0 Activated (set to '1') on completion of data transfer(s)
as specified by the descriptor's
CH_DESCR_CTL.INTR_TYPE.
1 SRC_BUS_ERROR RW1C RW1S 0 Activated (set to '1') on a bus error for a load from the
source.
2 DST_BUS_ERROR RW1C RW1S 0 Activated (set to '1') on a bus error for a store to the
destination.
3 SRC_MISAL RW1C RW1S 0 Activated (set to '1') on a misalignment of the source
address.
4 DST_MISAL RW1C RW1S 0 Activated (set to '1') on a misalignment of the
destination address.
5 CURR_PTR_NULL RW1C RW1S 0 Activated (set to '1') when the channel is enabled
(CH_CTL.ENABLED is '1') and CH_CURR_PTR is '0'.
6 ACTIVE_CH_DISABLED RW1C RW1S 0 Activated (set to '1') if the channel is disabled by SW
(accidentally/incorrectly) when the data transfer engine
is busy.
7 DESCR_BUS_ERROR RW1C RW1S 0 Activated (set to '1') on a bus error for a load of the
descriptor.
823
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers