Technical Reference Manual 002-29852 Rev. *B
4.13.11.16 CM4_TPIU_DEVID
Description:
Device ID
Address:
0xE008EFC8
Offset:
0xFC8
Retention:
Retained
IsDeepSleep:
No
Comment:
This register is implementation-defined for each Part Number and Designer. This indicates the
capabilities of the component. The entire 32-bit field can be used because the data width is
determined by the particular component. Unused bits must read as zero.
If the component is configurable then it is recommended that this register reflects any changes
to a standard configuration.
Default:
0xCA0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name CLKRELAT
[5:5]
MUXNUM [4:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:12] SWOUARTNR
Z [11:11]
SWOMAN
[10:10]
TCLKDATA
[9:9]
FIFOSIZE
[8:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:4 MUXNUM R R 0 Indicates the level of input multiplexing. When non-
zero, this value indicates the type of multiplexing on
the input to the ATB. Currently only 0x00 is supported,
that is, no multiplexing is present. This value helps
detect the ATB structure.
5 CLKRELAT R R 1 Indicates the relationship between atclk and traceclkin.
This bit is '1' indicating traceclkin can be asynchronos
to atclk.
6:8 FIFOSIZE R R 2 TPIU buffer size. This field value is 0b010 indicating 4
Bytes.
9 TCLKDATA R R 0 This bit Reads-As-Zero (RAZ), indicating that trace
data and clock modes are supported
10 SWOMAN R R 1 Indicates whether Serial Wire Output, Manchester
encoded format, is supported.
11 SWOUARTNRZ R R 1 Indicates whether Serial Wire Output, UART or NRZ, is
supported.
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers
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