Infineon TRAVEO T2G - 4.13.1.2 CM4_ITM_TER

Technical Reference Manual 002-29852 Rev. *B
4.13.1.2 CM4_ITM_TER
Description:
Trace Enable Register
Address:
0xE0000E00
Offset:
0xE00
Retention:
Retained
IsDeepSleep:
No
Comment:
The ITM_TERx characteristics are:
Purpose: Provide an individual enable bit for each ITM_STIM register.
Usage constraints
- Each ITM_TER provides enable bits for 32 ITM_STIM registers.
- Bits corresponding to unimplemented ITM_STIM registers are RAZ/WI. See Trace Privilege
Register, ITM_TPR on page C1-775 for information about the number of implemented
ITM_STIM registers.
- The processor ignores any unprivileged write to an ITM_TERx bit if the corresponding
ITM_TPR.PRIVMASK bit is set to 1, see Trace Privilege Register, ITM_TPR on Arm TRM
page C1-775.
Configurations: Always implemented.
Attributes: See Table C1-11 on page C1-773.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name STIMENA [7:0]
Bits 15 14 13 12 11 10 9 8
Name STIMENA [15:8]
Bits 23 22 21 20 19 18 17 16
Name STIMENA [23:16]
Bits 31 30 29 28 27 26 25 24
Name STIMENA [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:31 STIMENA RW R 0 For bit STIMENA[n]:
0: Stimulus port (n) disabled
1: Stimulus port (n) enabled
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2022-04-18
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