Infineon TRAVEO T2G - 19.5.1.9 PASS_SAR_TR_PEND

Technical Reference Manual 002-29852 Rev. *B
19.5.1.9 PASS_SAR_TR_PEND
Description:
Trigger pending status
Address:
0x40900100
Offset:
0x100
Retention:
Not Retained
IsDeepSleep:
No
Comment:
Status
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name TR_PEND [7:0]
Bits 15 14 13 12 11 10 9 8
Name TR_PEND [15:8]
Bits 23 22 21 20 19 18 17 16
Name TR_PEND [23:16]
Bits 31 30 29 28 27 26 25 24
Name TR_PEND [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:31 TR_PEND R W 0 Trigger Pending.
Hardware will set this bit if a hardware trigger is
received.
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2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers