Infineon TRAVEO T2G - 28.4.1.1.19 TCPWM_GRP_CNT_INTR

Technical Reference Manual 002-29852 Rev. *B
28.4.1.1.19 TCPWM_GRP_CNT_INTR
Description:
Interrupt request register
Address:
0x40380070
Offset:
0x70
Retention:
Not Retained
IsDeepSleep:
No
Comment:
The register fields are not retained. This is to ensure that they come up as '0' after coming out
of DeepSleep system power mode. HW clears the interrupt causes to '0', when the counter is
disabled.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:3] CC1
_MATCH
[2:2]
CC0
_MATCH
[1:1]
TC [0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits
Name SW HW Default or
Enum
Description
0 TC RW1C RW1S 0 Terminal count event. Set to '1', when event is
detected. Write with '1' to clear bit.
1 CC0_MATCH RW1C RW1S 0 Counter matches CC0 register event. Set to '1', when
event is detected. Write with '1' to clear bit.
2 CC1_MATCH RW1C RW1S 0 Counter matches CC1 register event. Set to '1', when
event is detected. Write with '1' to clear bit.
1819
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers