Infineon TRAVEO T2G - 2.3.9.6.45 CANFD_CH_TXEFS

Technical Reference Manual 002-29852 Rev. *B
2.3.9.6.45 CANFD_CH_TXEFS
Description:
Tx Event FIFO Status
Address:
0x405200F4
Offset:
0xF4
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:6] EFFL [5:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:13] EFGI [12:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:21] EFPI [20:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:26] TEFL
[25:25]
EFF [24:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:5 EFFL R RW 0 Event FIFO Fill Level
Number of elements stored in Tx Event FIFO, range 0
to 32.
8:12 EFGI R RW 0 Event FIFO Get Index
Tx Event FIFO read index pointer, range 0 to 31.
16:20 EFPI R RW 0 Event FIFO Put Index
Tx Event FIFO write index pointer, range 0 to 31.
24 EFF R RW 0 Event FIFO Full
0= Tx Event FIFO not full
1= Tx Event FIFO full
25 TEFL R RW 0 Tx Event FIFO Element Lost
This bit is a copy of interrupt flag IR.TEFL. When
IR.TEFL is reset, this bit is also reset.
0= No Tx Event FIFO element lost
1= Tx Event FIFO element lost, also set after write
attempt to Tx Event FIFO of size zero.
102
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers