Infineon TRAVEO T2G - 26.8.8 SRSS_INTR

Technical Reference Manual 002-29852 Rev. *B
26.8.8 SRSS_INTR
Description:
SRSS Interrupt Register
Address:
0x40260200
Offset:
0x200
Retention:
Retained
IsDeepSleep:
Yes
Comment:
Interrupt signal from SRSS includes this register and also BACKUP_INTR, if present.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:6] CLK_CAL
[5:5]
None [4:3] HVLVD2
[2:2]
HVLVD1
[1:1]
None [0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
1 HVLVD1 RW1C A 0 Interrupt for low voltage detector HVLVD1
2 HVLVD2 RW1C A 0 Interrupt for low voltage detector HVLVD2
5 CLK_CAL RW1C A 0 Clock calibration counter is done. This field is reset
during DEEPSLEEP mode.
1638
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers