Technical Reference Manual 002-29852 Rev. *B
21.504.2.11 PERI_MS_PPU_FX_MS_ATT2
Description:
Master attributes 2
Address:
0x40010838
Offset:
0x38
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x1F1F1F1F
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:5] PC8_NS
[4:4]
PC8_PW
[3:3]
PC8_PR
[2:2]
PC8_UW
[1:1]
PC8_UR
[0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:13] PC9_NS
[12:12]
PC9_PW
[11:11]
PC9_PR
[10:10]
PC9_UW
[9:9]
PC9_UR
[8:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:21] PC10_NS
[20:20]
PC10_PW
[19:19]
PC10_PR
[18:18]
PC10_UW
[17:17]
PC10_UR
[16:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:29] PC11_NS
[28:28]
PC11_PW
[27:27]
PC11_PR
[26:26]
PC11_UW
[25:25]
PC11_UR
[24:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 PC8_UR R R 1 Protection context 8, user read enable.
1 PC8_UW RW R 1 Protection context 8, user write enable.
2 PC8_PR R R 1 Protection context 8, privileged read enable.
3 PC8_PW RW R 1 Protection context 8, privileged write enable.
4 PC8_NS RW R 1 Protection context 8, non-secure.
8 PC9_UR R R 1 Protection context 9, user read enable.
9 PC9_UW RW R 1 Protection context 9, user write enable.
10 PC9_PR R R 1 Protection context 9, privileged read enable.
11 PC9_PW RW R 1 Protection context 9, privileged write enable.
12 PC9_NS RW R 1 Protection context 9, non-secure.
16 PC10_UR R R 1 Protection context 10, user read enable.
17 PC10_UW RW R 1 Protection context 10, user write enable.
18 PC10_PR R R 1 Protection context 10, privileged read enable.
19 PC10_PW RW R 1 Protection context 10, privileged write enable.
20 PC10_NS RW R 1 Protection context 10, non-secure.
24 PC11_UR R R 1 Protection context 11, user read enable.
25 PC11_UW RW R 1 Protection context 11, user write enable.
26 PC11_PR R R 1 Protection context 11, privileged read enable.
27 PC11_PW RW R 1 Protection context 11, privileged write enable.
28 PC11_NS RW R 1 Protection context 11, non-secure.
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers
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