Infineon TRAVEO T2G - 8.5.3.19 DMAC_CH_INTR_MASKED

Technical Reference Manual 002-29852 Rev. *B
8.5.3.19 DMAC_CH_INTR_MASKED
Description:
Interrupt masked
Address:
0x402A108C
Offset:
0x8C
Retention:
Not Retained
IsDeepSleep:
No
Comment:
When read, this register reflects a bitwise AND between the INTR and INTR_MASK registers.
This register allows SW to read the status of all mask enabled interrupt causes with a single
load operation, rather than two load operations: one for INTR and one for INTR_MASK. This
simplifies Firmware development. The associated interrupt is active ('1'), when
INTR_MASKED != 0.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name DESCR
_BUS
_ERROR
[7:7]
ACTIVE
_CH
_DISABLED
[6:6]
CURR_PTR
_NULL [5:5]
DST
_MISAL
[4:4]
SRC
_MISAL
[3:3]
DST_BUS
_ERROR
[2:2]
SRC_BUS
_ERROR
[1:1]
COMPLETIO
N [0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 COMPLETION R W 0 Logical and of corresponding INTR.COMPLETION and
INTR_MASK.COMPLETION fields.
1 SRC_BUS_ERROR R W 0 Logical and of corresponding
INTR.SRC_BUS_ERROR and
INTR_MASK.SRC_BUS_ERROR fields.
2 DST_BUS_ERROR R W 0 Logical and of corresponding
INTR.DST_BUS_ERROR and
INTR_MASK.DST_BUS_ERROR fields.
3 SRC_MISAL R W 0 Logical and of corresponding INTR.SRC_MISAL and
INTR_MASK.SRC_MISAL fields.
4 DST_MISAL R W 0 Logical and of corresponding INTR.DST_MISAL and
INTR_MASK.DST_MISAL fields.
5 CURR_PTR_NULL R W 0 Logical and of corresponding INTR.CURR_PTR_NULL
and INTR_MASK.CURR_PTR_NULL fields.
6 ACTIVE_CH_DISABLED R W 0 Logical and of corresponding
INTR.ACTIVE_CH_DISABLED and
INTR_MASK.ACTIVE_CH_DISABLED fields.
7 DESCR_BUS_ERROR R W 0 Logical and of corresponding
INTR.DESCR_BUS_ERROR and
INTR_MASK.DESCR_BUS_ERROR fields.
826
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers