Infineon TRAVEO T2G - 19.1.20 CH 19; 19.1.21 CH 20; 19.1.22 CH 21; 19.1.23 CH 22

Technical Reference Manual 002-29852 Rev. *B
Register Name Address Permission Description
PASS0_SAR0_CH18_TR_CTL
0x40900C80 FULL Trigger control.
PASS0_SAR0_CH18_SAMPLE_CTL
0x40900C84 FULL Sample control.
PASS0_SAR0_CH18_POST_CTL
0x40900C88 FULL Post processing control
PASS0_SAR0_CH18_RANGE_CTL
0x40900C8C FULL Range thresholds
PASS0_SAR0_CH18_INTR
0x40900C90 FULL Interrupt request register.
PASS0_SAR0_CH18_INTR_SET
0x40900C94 FULL Interrupt set request register
PASS0_SAR0_CH18_INTR_MASK
0x40900C98 FULL Interrupt mask register.
PASS0_SAR0_CH18_INTR_MASKED
0x40900C9C FULL Interrupt masked request register
PASS0_SAR0_CH18_WORK
0x40900CA0 FULL Working data register
PASS0_SAR0_CH18_RESULT
0x40900CA4 FULL Result data register
PASS0_SAR0_CH18_GRP_STAT
0x40900CA8 FULL Group status register
PASS0_SAR0_CH18_ENABLE
0x40900CB8 FULL Enable register
PASS0_SAR0_CH18_TR_CMD
0x40900CBC FULL Software triggers
19.1.20 CH 19
Register Name Address Permission Description
PASS0_SAR0_CH19_TR_CTL
0x40900CC0 FULL Trigger control.
PASS0_SAR0_CH19_SAMPLE_CTL
0x40900CC4 FULL Sample control.
PASS0_SAR0_CH19_POST_CTL
0x40900CC8 FULL Post processing control
PASS0_SAR0_CH19_RANGE_CTL
0x40900CCC FULL Range thresholds
PASS0_SAR0_CH19_INTR
0x40900CD0 FULL Interrupt request register.
PASS0_SAR0_CH19_INTR_SET
0x40900CD4 FULL Interrupt set request register
PASS0_SAR0_CH19_INTR_MASK
0x40900CD8 FULL Interrupt mask register.
PASS0_SAR0_CH19_INTR_MASKED
0x40900CDC FULL Interrupt masked request register
PASS0_SAR0_CH19_WORK
0x40900CE0 FULL Working data register
PASS0_SAR0_CH19_RESULT
0x40900CE4 FULL Result data register
PASS0_SAR0_CH19_GRP_STAT
0x40900CE8 FULL Group status register
PASS0_SAR0_CH19_ENABLE
0x40900CF8 FULL Enable register
PASS0_SAR0_CH19_TR_CMD
0x40900CFC FULL Software triggers
19.1.21 CH 20
Register Name Address Permission Description
PASS0_SAR0_CH20_TR_CTL
0x40900D00 FULL Trigger control.
PASS0_SAR0_CH20_SAMPLE_CTL
0x40900D04 FULL Sample control.
PASS0_SAR0_CH20_POST_CTL
0x40900D08 FULL Post processing control
PASS0_SAR0_CH20_RANGE_CTL
0x40900D0C FULL Range thresholds
PASS0_SAR0_CH20_INTR
0x40900D10 FULL Interrupt request register.
PASS0_SAR0_CH20_INTR_SET
0x40900D14 FULL Interrupt set request register
PASS0_SAR0_CH20_INTR_MASK
0x40900D18 FULL Interrupt mask register.
PASS0_SAR0_CH20_INTR_MASKED
0x40900D1C FULL Interrupt masked request register
PASS0_SAR0_CH20_WORK
0x40900D20 FULL Working data register
PASS0_SAR0_CH20_RESULT
0x40900D24 FULL Result data register
PASS0_SAR0_CH20_GRP_STAT
0x40900D28 FULL Group status register
PASS0_SAR0_CH20_ENABLE
0x40900D38 FULL Enable register
PASS0_SAR0_CH20_TR_CMD
0x40900D3C FULL Software triggers
19.1.22 CH 21
Register Name Address Permission Description
PASS0_SAR0_CH21_TR_CTL
0x40900D40 FULL Trigger control.
PASS0_SAR0_CH21_SAMPLE_CTL
0x40900D44 FULL Sample control.
PASS0_SAR0_CH21_POST_CTL
0x40900D48 FULL Post processing control
PASS0_SAR0_CH21_RANGE_CTL
0x40900D4C FULL Range thresholds
PASS0_SAR0_CH21_INTR
0x40900D50 FULL Interrupt request register.
PASS0_SAR0_CH21_INTR_SET
0x40900D54 FULL Interrupt set request register
PASS0_SAR0_CH21_INTR_MASK
0x40900D58 FULL Interrupt mask register.
PASS0_SAR0_CH21_INTR_MASKED
0x40900D5C FULL Interrupt masked request register
PASS0_SAR0_CH21_WORK
0x40900D60 FULL Working data register
PASS0_SAR0_CH21_RESULT
0x40900D64 FULL Result data register
PASS0_SAR0_CH21_GRP_STAT
0x40900D68 FULL Group status register
PASS0_SAR0_CH21_ENABLE
0x40900D78 FULL Enable register
PASS0_SAR0_CH21_TR_CMD
0x40900D7C FULL Software triggers
19.1.23 CH 22
1076
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers